Phase detectors are logic circuits used to generate pump-up and pump-down signals to control charge-pump circuits in a clock and data recovery PLL. Phase detectors can also generate recovered-data. As operating speeds of clock and data recovery units increase, the design of voltage-controlled oscillators and charge pump circuits becomes complicated and highly power consuming. The use of half-rate clock phase detectors can reduce the complexity and power demand of the associated charge pump circuits and voltage controlled oscillators.
Referring to FIG. 1, a circuit 10 illustrates a current architecture for a half-rate clock phase detector. The circuit 10 comprises a number of D flip-flops 12a-12g, a selector circuit 14, a selector circuit 16, an XOR gate 18 and an XOR gate 20.
The phase detector 10 generates a pump-up signal by first generating two internal pump-up signals 22, 24 and dynamically selecting one to be the final pump-up signal using a clock sampled by data as a reference. The phase detector 10 responds to only one edge of data transitions. Thus, to perform phase detection using both edges, four internal pump-up signals would have to be generated (two for each rising edge and two for each falling edge). The phase detector 10 may require an excessive number of gates due to the replication of the circuit to retain information in all data edges. The additional gates imply more power consumption and more space.